Current phase-locked loop (PLL) circuits may include features for comparing the phase of an output signal from a voltage-controlled oscillator (VCO) with the phase of an input reference frequency to the PLL. Such circuits may include a phase frequency detector for producing an error signal that signifies the proportion of any phase difference between the output signal and the input reference frequency. In addition, current PLL circuits may also include features for feeding the error signal into a low-pass filter and then into the VCO such that the output signal that is produced is synchronized with the input reference frequency to the PLL. Current PLL circuits may employ the negative feedback loop method of feeding the output from the VCO back into the input of the phase frequency detector such that an error signal may be generated, coupling the output signal from the VCO to the input reference frequency. In some current PLL circuits, the output signal may be fed into a frequency divider circuit to produce an integer multiple of the input reference frequency. When the phase-lock condition is reached, the output signal from the VCO is equal to N times the input reference frequency, where N is the division ratio of the frequency divider circuit. Accordingly, current PLL circuits generate frequencies only at integer multiples of the input reference frequency.
Those frequency synthesizers can only generate a frequency at an integer multiple of the input reference frequency. To circumvent such restriction, the frequency synthesizer may further include a ΣΔ modulator to modulate the value of the division per frequency cycle to obtain a fractional value. Such a frequency synthesizer is called a fractional-N frequency synthesizer. The fractional-N frequency synthesizer can generate signals whose frequency is of the form:
            F      vco        =                  F        reference            ×              (                  INT          +                      FRAC            MOD                          )              ,where INT, FRAC, and MOD are integers, and FVCO is thus not necessarily an integer multiple of the reference frequency Freference. Existing ΣΔ modulation may continuously create time differences at the input of the phase frequency detector, which in turn are converted into charge quantities by the charge-pump. The ΣΔ modulator shapes the fractional-N modulation power towards the high frequencies and, by doing so, shifts the degrading, extra noise outside the bandwidth of the loop filter of the feedback loop, causing the extra noise to be filtered out. The conversion from time differences at the phase frequency detector input into charge quantities in the loop filter may be performed in a highly linear manner such that the noise-shaping, spectral properties that result from using the ΣΔ modulator are not altered such that some noise is, as a consequence, introduced into the PLL loop. Preventing such noise from being introduced into the PLL loop maintains the phase-noise performance that results from using fractional-N modulation implemented with a frequency divider and ΣΔ modulator. In other words, in order to prevent degradation of phase-noise spectral properties, especially in a fractional-N PLL synthesizer, various types of ΣΔ modulator noise shaping techniques may be known for this purpose; however, a highly linear conversion method from a detected phase deference at a phase frequency detector into charge quantities on the loop filter, connected to VCO, is not known.